1. Field of the Invention
The invention relates to a phase locked loop that can obtain an output frequency of more precise frequency resolution than a reference frequency making use of a fraction frequency division, and relates particularly to a phase locked loop that includes a memory for storing a dividing value with a less capacity.
2. Description of Related Art
The phase locked loop (PLL) is generally meant by an electronic circuit in which a frequency of an output signal is made identical to that of an input signal or a reference frequency. When a dividing value is switched over to another one using this type of fraction division, noise is produced in switching the values.
In order to solve this noise problem, there has been proposed a noise shaping system. According to the noise shaping system, ΣΔ (sigma-delta) modulation is used to make the noise present in a broader frequency band, which moves unnecessary noise components to a higher frequency region than a signal band. The noise shaping system can quantize a signal producing almost no quantization error. As a document that discloses the phase locked loop employing the noise shaping system, Japanese Unexamined Publication No. 2002-16494 can be cited.
By the way, the phase locked loop of the prior art includes a method by which a dividing value is calculated whenever an output of a variable frequency divider varies, and a method by which a dividing value is read out for its use from a memory at the time of a frequency division after the dividing value is calculated and stored beforehand in the memory.
Referring to FIG. 6, an explanation is given below that is about a method for calculating a dividing value in advance described in the patent document above. In FIG. 6, a phase locked loop 10 contains an arithmetic circuit 1, a memory circuit 2, a variable frequency divider 3, an address generator 4, a phase comparator 5, a low pass filter (LPF) 6, and a voltage controlled oscillator 7. The memory circuit 2 stores dividing values using different addresses for necessary frequencies. The dividing values to be stored are represented as follows.
The dividing value=N+L/A,
where N, L and A are an integer, N is an integer portion of the dividing value, L is a numerator of a fraction, and A is a denominator of the fraction.
Next, an operation of FIG. 6 will be explained. The arithmetic circuit 1 calculates a dividing value in advance according to an output frequency of the variable frequency divider 3, and outputs the dividing value to the memory circuit 2, which stores the dividing value from the arithmetic circuit 1. To the address generator 4 is input a signal from an input unit (not shown). Using this signal and a clock signal from the variable frequency divider 3, a reading-out address in the memory circuit 2 is specified.
The variable frequency divider 3 applies the clock signal to the phase comparator 5 which compares a reference frequency with the clock signal from the variable frequency divider 3. The LPF 6 eliminates higher frequency components of a signal from the phase comparator 5 to provide lower frequency components of the signal to the voltage controlled oscillator 7 which, in response to the voltage from the LPF 6, varies an oscillation frequency to be supplied to the variable frequency divider 3.
Incidentally, a dividing value to be stored in the memory circuit 2 is determined by the integer portion N and the fraction portion (L/A). With respect to the data needed as the dividing value, A data are required for one integer portion N. For example, when the integer portion N needs 32, 32 * A are necessary as the dividing value.
Under the situation, since the integer portion N is decided based on a variable scope of the output frequency, a short variable scope causes no problem.
However, since the variable scope of the output frequency of the variable frequency divider 3 of a phase locked loop that is used in a frequency synthesizer is wide, the integer portion N is large. Accordingly, the conventional system required the memory circuit 2 to have an immense capacity in order to store dividing values.
On the other hand, when a method of calculating a dividing value is adopted every time an output of the variable frequency divider varies, so as to solve the problem, another problem is caused that calculation time becomes longer.